As is well known, microprocessors often are defined in a single semiconductor chip comprising an arrangement of electronic components defining control, logic and datapath portions. The latter portion includes a central processing unit (CPU) in which data is processed under the control of the control portion. Frequently the CPU along with limited datapath and control functions, is defined on a separate chip linked into a system with other chips to form a microprocessor chipset. Each of these other chips also includes an arrangement of electronic components which may perform a different function such as system input-output (I/O), direct memory access (DMA) control, interrupt and memory management (MMU), many of which functions could have been incorporated into a single microprocessor chip of limited capability. The chips cooperate to provide an augmented capability when compared to such a single microprocessor chip.
As is the case with the synchronization of the various functional components on a single chip, the components of all the chips in a chipset must be synchronized as well. A separate clock chip provides clock pulses for synchronizing the various components in the several chips. But, inside each chip, skew still frequently occurs in the clock pulses due to capacitive loading and similar effects as is well understood. Because such skew makes the time reference of each chip different, skew results in a lowering of frequency of operation of the chipset.
Efforts have been made to reduce clock pulse skew in chipsets. In one instance, different voltage levels are provided to different chips. The different voltage levels produce different currents which change the switching speeds in the different chips. But this expedient requires additional circuitry and results in undesirable changes in the operating parameters of the various chips.